The invention pertains to an MOS memory device. More specifically, the invention pertains to a dynamic-type MOS RAM (Random Access Memory) which has a non-volatile back-up storage capability.
A great deal of research activity has recently been conducted to develop a non-volatile random access memory on a single silicon chip. Prior to the availability of non-volatile random access memories fabricated on a single silicon chip, the most common way of achieving non-volatility was to provide a battery backup for the MOS memory. When a main power supply failed, the battery was automatically switched in to power the device until the main power source could be brought back on-line. This arrangement was generally not satisfactory because the battery was expensive, the battery required periodic maintenance and replacement and, if the battery failed, the data stored in the memory was disastrously lost. For these reasons, it is desirable to provide a non-volatile random access memory which does not require a battery back-up.
A non-volatile memory device fabricated on a single silicon chip is disclosed in "Dual-Electron Injector-Structure Electrically Alterable Read-Only Memory Model Studies," DiMaria et al., IEEE Transactions on Electron Devices, Vol. ED-28, No. 9, September 1981, and in copending patent application Ser. No. 124,003, filed Feb. 26, 1980, which is assigned in common with the present application. This memory device uses a cell structure composed of an n-channel MOS transistor with DEIS (Dual Electron Injector Stack) material positioned between a control gate and a "floating" polycrystalline silicon gate. Writing is performed by applying a negative voltage to the control gate. This negative voltage causes the injection of electrons from the top silicon-rich SiO.sub.2 injector layer of the DEIS material to the floating polysilicon layer. Similarly, erasing is performed by applying a positive voltage to the control gate, which then injects electrons from a bottom silicon-rich SiO.sub.2 injector layer of the DEIS material to the floating polysilicon layer.
As shown in FIG. 4A, the DEIS material is formed by a layer 42 of insulating SiO.sub.2 sandwiched between two silicon-rich SiO.sub.2 injector layers 41 and 43. Polysilicon layers are located immediately outside the silicon-rich SiO.sub.2 injector layers, the lower one of which forms the floating gate electrode and the upper one of which is connected to a gate line. The log I-V.sub.CS characteristic of this material is shown in FIG. 4B. When a positive voltage V.sub.CS of sufficient magnitude is applied, the current through the material is I=I.sub.OP e.sup.K P.sup.V CS, while when a negative voltage V.sub.CS of sufficient magnitude is applied across the device, a negative current I=I.sub.ON e.sup.K N.sup.V CS will flow, where I.sub.OP, I.sub.ON, K.sub.P and K.sub.N are constants. Otherwise, when the magnitude of the voltage V.sub.CS is sufficiently low, substantially no current will flow through the material.
While the memory device of the DiMaria et al. publication does in fact provide non-volatile storage capability and is quite useful in a number of applications, it is still not acceptable for many applications in which random access memories have customarily been employed. The reasons are that the relatively long reading and writing times are required to get data in and out of the memory cells. Moreover, there is a serious drawback in that only a limited number (for instance, 10,000) reading and writing operations can be performed in a cell of this type.
To achieve higher normal operating speeds while retaining a non-volatile memory capability, several proposals have been made to pair non-volatile backup storage cells with faster storage cells which do not have the non-volatile storage capability. During normal continuous operations, the memory operates using the volatile cells. If the power supply fails, back-up power is supplied for a relatively short period of time from a storage source such as a capacitor bank. As soon as the main power supply fails, data from the volatile cells is transferred to their paired non-volatile cells using the power from the back-up power source. When the normal power source is back on-line, a data transfer operation is made from the non-volatile cells back to the volatile cells, and then normal memory operation is continued. Examples of memories of this type are described in the articles "Five Volt Only Non-Volatile RAM Owes It All To Polysilicon," Electronics, Oct. 11, 1979, p 111, "Completely Electrically Erasible Memory Behaves Like A fast, Non-Volatile RAM," Electronics, May 10, 1979, p. 128 and co-pending U.S. patent application Ser. Nos. 192,579 and 192,580 filed Sept. 30, 1980 and assigned in common herewith.
Although the devices of these proposals do provide an increased minimum operating speed together with non-volatile storage for use during times of power failure, the density of the memory cells is not attractive on a cost/performance basis compared to a battery powered volatile random access memory arrangement. This is in large part due to the use of static-type memory cells for the volatile cells of the memory. As is well known, static MOS memory cells use a two-transistor flip-flop arrangement requiring a relatively large amount of chip surface area per cell.
In many applications, it is preferable to provide a random access memory utilizing dynamic cells. The reason for this is that much higher cell densities are obtainable, although at the cost of having to periodically refresh the cells. A memory of this type is described in the article "64-K Dynamic RAM Needs Only One 5-Volt Supply to Outstrip 16-K Parts," Electronics, Sept. 28, 1978. Each memory cell in this random access memory device requires only a single MOS transistor and storage capacitor. However, the memory described in this article has no non-volatile data capability.
U.S. Pat. No. 4,055,837, issued Oct. 25, 1977 to Stein et al., describes a dynamic single transistor memory element which provides for relative-permanent storage. The memory cell of the memory array is composed of an MOS transistor having a gate coupled to a word line and a source and drain coupled in series with a metal dielectric semiconductor capacitor between a write line and a bit line. This arrangement suffers from a drawback in that, to recommence normal operations following restoration of power, it is necessary to perform a restore operation. This restore operation erases the data from non-volatile storage. Thus, the device has no latent storage capability. That is, the device is not capable of retaining a primary set of data in its nonvolatile storage cells after a restore operation has been performed.
A further example of a dynamic memory having a non-volatile storage capability but with no latent image capability is disclosed in commonly-assigned U.S. Pat. application Ser. No, 219,285, filed Dec. 22, 1980.
Thus, it is a primary object of the present invention to provide a high speed MOS memory device having non-volatile backup storage capability.
Further, it is an object of the present invention to provide such a memory device in which, in addition to the non-volatile storage capability, a latent storage capability is also provided.
It is yet a further object of the present invention to provide such a memory device having a very small cell size and simple and construction.
It is also an object of the present invention to provide a method of operating such a memory device.